A nonvolatile semiconductor memory device disclosed in Japanese Patent Publication No. 2005-25914 has such a constitution as a memory cell 110 is formed by connecting one end of a variable resistor element with the drain of a selector transistor, while a plurality of the memory cells are arranged in rows and columns to form a memory array 1010, as shown in FIG. 8. The plurality of memory cells disposed in one row are connected to a word line at the gate of the selector transistor, and the plurality of memory cells disposed in one column are connected to a bit line at the other end of the variable resistor element. The plurality of memory cells 110 disposed in one row or in one column are connected to a source line at the source of the selector transistor.
However, the prior art technology described above has such a constitution as the memory cell 110 formed by connecting the variable resistor element and the selector transistor is provided for each bit of information, while the word line, the bit line and the source line are connected to each memory cell 110.
In the prior art technology described above, the memory cell 110 is used as the basic unit, with a plurality of the memory cells 110 arranged in a matrix of rows and columns so as to form the memory array 1010. This constitution is well known in the field of randomly accessible storage devices such as DRAM or NOR type flash memory. A storage device having this constitution uses each memory cell as the basic unit, while the word line, the bit line and the source line are connected to each memory cell, thus resulting in restraint on the degree of integration with respect to the circuit layout.
For example, the circuit layout requires it to connect the variable resistor element that constitutes the memory cell 110 and the selector transistor by means of a contact layer and secure a contact region in accordance to the layout of the contact layer. In addition, it is necessary to secure a contact region for connecting the memory cell 110 to each of the word line, the bit line and the source line. This means that four contact regions must be provided for each of the memory cells 110. The four contact regions and the requirements imposed on the circuit layout by the constitution of the memory array 1010 may restrict the improvement in the degree of integration.